A phase lock loop (PLL) is a control system that generates an output signal having a phase that is related to a phase of an input signal. PLLs may include multiple voltage controlled oscillators (VCOs) to support multiple frequency ranges. A VCO having a desired frequency range may be selected by a selection device, such as a footer device.
The selection device does not contribute to oscillation, yet adds to manufacturing costs and parasitic resistance. Moreover, extreme frequencies (e.g., above 22 GHz) may result in high resistance in the contacts, vias, and wires of a VCO. The frequency extremes may also result in startup problems. For example, a VCO may fail to initiate oscillation.